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Resets - make them synchronous and local

A common approach to resets in a design is to have one single global asynchronous reset network. In this post, I will argue why this is a bad idea, and why you should in fact do the exact opposite, by implementing a reset strategy that is:

  • synchronous - not asynchronous
  • local - not global

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Xilinx implementation properties for timing performance

Below I have listed the Xilinx implementation properties I use when giving priority to timing rather than area. Settings not mentioned are not as important, or are recommended to be given the default value.

"Exp." means experiment, that is, for that property it might be worth to try with different settings.

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RLOC attributes on inferred logic

The Xilinx constraint RLOC - relative placement - can be very helpful to improve the timing of timing-critical logic.

There is some struggle involved with getting the RLOC's recognized by the Xilinx tools if we wish to enter them through the HDL and on inferred logic rather than on instantiated primitives.

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Xilinx ISE silent/unattended install

System administrators might find it useful to be able to install Xilinx ISE software silently, without GUI and without having to interact with the install process. This post describes how to use the batch mode installer that Xilinx provides, and how to apply a certain trick needed to make the install truly silent.

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