When designing complex designs, I have come to use assertions more and more often. I've seen their benefits, and in my own design I have tried to get the most out of them by extending their traditional use. I thought I'd share my experiences and thoughts on these matters.

At first some short general notes on assertions. Assertions in VHDL is a means of producing an error at run-time if some condition is not met 1. An assertion for the signal err looks like this:

assert err='0' report "err/='0' in myUnit" severity error;

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Notes:

  1. Assertions in Verilog can be achieved through SystemVerilog/OVL.