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All posts tagged verification

Assertions - extending their use

September 5, 2012 carl Coding practice, Simulation, VHDL 1 Comment

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On this blog, I write about FPGA and HDL development philosophy along with various other topics such as VHDL language constructs, FPGA timing performance, FPGA tools and others.

I have been working most recently for Stockholm University where I have been a hardware developer for the IceCube Neutrino Telescope.

If you want to contact me, feel free to drop me an email on carl@wernhoff.com.

Categories

  • Altera tools
  • C programming
  • Coding practice
  • Miscellaneous
  • Simulation
  • Timing
  • VHDL
  • Xilinx tools

Tags

bufg bugs component configuration constraints distribution entity exponential fpga git greece hdl ise less lesspipe poisson reset rloc silent install source-highlight statistics syntax coloring synthesis tdd unit testing verification vhdl xilinx

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