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Resets - make them synchronous and local

A common approach to resets in a design is to have one single global asynchronous reset network. In this post, I will argue why this is a bad idea, and why you should in fact do the exact opposite, by implementing a reset strategy that is:

  • synchronous - not asynchronous
  • local - not global

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Assertions - extending their use

When designing complex designs, I have come to use assertions more and more often. I've seen their benefits, and in my own design I have tried to get the most out of them by extending their traditional use. I thought I'd share my experiences and thoughts on these matters.

At first some short general notes on assertions. Assertions in VHDL is a means of producing an error at run-time if some condition is not met 1. An assertion for the signal err looks like this:

assert err='0' report "err/='0' in myUnit" severity error;

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  1. Assertions in Verilog can be achieved through SystemVerilog/OVL.

Properly time-distributed stimuli - Part III

A use case example

I was working on a project in which not only the input data was time-stamped, but moreover, the density of the timestamps greatly affected the computation delay in terms of clock cycles. The project was performance critical and careful models of performance were needed. A very careful generation of the time stamps according to an appropriate model was necessary for the simulations to give us the results we needed, and to finally verify our performance models.

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Properly time-distributed stimuli - Part II

Basics about statistical distributions for events random in time

Poisson Process

We will study the case of the input events being described by a Poisson Process, the most common case for events random in time.

Without going into mathematical formalism, roughly described, events adhering to the following conditions can be labeled to be generated by a Poission Process:

  • The time of an event is independent of the time of the previous event
  • The events have a fixed average rate

Some examples of phenomena well-modeled by a Poisson Process are:

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Properly time-distributed stimuli - Part I

Introduction and summary

Finding any bugs or problems in simulations rather than in hardware tests is generally a big time-saver. Some designs will depend on how external input are distributed in time (control signals, input data write/fetches or time-stamped data) and in those cases a good model for those events is sometimes desired.

For events "random in time", we will see that the so-called Poisson Process-related distributions such as the Exponential or the Poisson Distribution can be used. We will also see that time deltas or absolute times of such distributions can be generated rather easily and computing-efficient.

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Xilinx implementation properties for timing performance

Below I have listed the Xilinx implementation properties I use when giving priority to timing rather than area. Settings not mentioned are not as important, or are recommended to be given the default value.

"Exp." means experiment, that is, for that property it might be worth to try with different settings.

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Operations on vectors with aggregate expressions

Say you have eight counters, each giving a status bit telling if it is actively counting or not, and that these status bits are brought together into a bit_vector called isCounting:

signal isCounting: bit_vector(7 downto 0);

Typically, you might want to perform bit operations on such a vector, like OR-ing or AND-ing all the bits, to see if any counter or all counters, respectively, are counting. Assume we want to OR the bits of isCounting into signal atLeastOneIsCounting:

OR into isCounting

This can of course be achieved through a process, e.g.:

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VHDL entity instantiation: why and how

In the days of the ancient Greeks there was component instantiation. Since then (the other parts of) the world has developed and VHDL'93 gave us entity instantiation. Most of you might already be using it, but for those who don't, I'd advise you to keep on reading.

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RLOC attributes on inferred logic

The Xilinx constraint RLOC - relative placement - can be very helpful to improve the timing of timing-critical logic.

There is some struggle involved with getting the RLOC's recognized by the Xilinx tools if we wish to enter them through the HDL and on inferred logic rather than on instantiated primitives.

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