Introduction and summary
Finding any bugs or problems in simulations rather than in hardware tests is generally a big time-saver. Some designs will depend on how external input are distributed in time (control signals, input data write/fetches or time-stamped data) and in those cases a good model for those events is sometimes desired.
For events "random in time", we will see that the so-called Poisson Process-related distributions such as the Exponential or the Poisson Distribution can be used. We will also see that time deltas or absolute times of such distributions can be generated rather easily and computing-efficient.
I'll walk you through the details, and and at the end exemplify with a use case from a project I was working on.
Modeling simulation stimuli
Simulating a design requires stimuli. For good reasons, much work is often put into what stimuli/input data to generate, but more seldom, a careful model of when the data or some control signal is sent to the design is utilized. In other words, how am I to separate write/fetch operations in time - with what number of clock flanks of delay?
These issues can appear in three respects:
- For data processing-centered designs (input data words appear random in time) - how to set the number of clock flanks between consecutive write/fetch operations
- For designs depending on external control signals (the control signal changes are random in time) - the control signals might be an interrupt request, a user input or anything else
- For designs processing time-stamped data (the values of the time-stamps are randomly distributed in time)
Time-stamped data appears e.g. in data taking applications, and also sometimes in network packets 1.
For any of the three points above, the events will sometimes be scheduled, or for some other reason will not be random in its nature, and then the methods here won't really apply.
Using the model in the simulation
Once a model exists, using it of course requires the test bench, or more generally the method used of presenting stimuli to the design, to be able to follow such a model. This can be solved in a number of ways, whether using text-file based input, Matlab's EDA Simulator Link, a TCL-file with
force commands (in the case of ModelSim) or some other method.
Benefits and uses
Finding bugs and problems
Generally I'd say that spending time on making the simulations mimic reality is well worth it, because of the ease of debugging and trouble-shooting simulations compared with hardware tests (if anyone else than me ever spent a week or more digging deep into a complex design with ChipScope, or any other Logic Analyzer, to trouble-shoot hardware bugs, you know what I'm talking about).
Extending the scope of simulations
The classical use of simulations is to check the output of a unit given a certain input. With properly time-distributed input data, the simulation can also generate more time-domain oriented characteristics such as
- buffer occupancy (input/output/intermediate buffers),
- the throughput of the unit and
- the delay of the unit
Comparing such measures to requirements, or estimates/models can help to identify problems earlier in the design phase.
Go on to Part II ->
- TCP packets have an optional time stamp, but be aware that since these time stamps are often used only for resolving packet order, the sender might only tick it up by 1 for each sent packet; see http://tools.ietf.org/html/rfc1323 ↩