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Infering dual-port BlockRam with XST

Getting XST (Xilinx' synthesis tool) to infer RAM or ROM that is dual-port requires some tricks.

For some reason, the two ports must be described by separate processes. Furthermore, an unusual VHDL construct, a shared variable, is needed 1.

Below is a listing of my parameterized module for dual-port RAM. It will successfully infer dual-port RAM, as desired, with XST. Remove the write enable-signals and write logic to get ROM instead of RAM. Specify width and depth with width and highAddr (highAddr is one less than desired depth) generics.

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  1. The variable must be accessible through two different processes, and hence must be shared. A signal wouldn't have worked; to implement write-first behaviour in a convenient way, a variable must be used, since the data written must be accessible on the next line of code.

Xilinx implementation properties for timing performance

Below I have listed the Xilinx implementation properties I use when giving priority to timing rather than area. Settings not mentioned are not as important, or are recommended to be given the default value.

"Exp." means experiment, that is, for that property it might be worth to try with different settings.

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RLOC attributes on inferred logic

The Xilinx constraint RLOC - relative placement - can be very helpful to improve the timing of timing-critical logic.

There is some struggle involved with getting the RLOC's recognized by the Xilinx tools if we wish to enter them through the HDL and on inferred logic rather than on instantiated primitives.

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Xilinx ISE silent/unattended install

System administrators might find it useful to be able to install Xilinx ISE software silently, without GUI and without having to interact with the install process. This post describes how to use the batch mode installer that Xilinx provides, and how to apply a certain trick needed to make the install truly silent.

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