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Assertions - extending their use

When designing complex designs, I have come to use assertions more and more often. I've seen their benefits, and in my own design I have tried to get the most out of them by extending their traditional use. I thought I'd share my experiences and thoughts on these matters.

At first some short general notes on assertions. Assertions in VHDL is a means of producing an error at run-time if some condition is not met 1. An assertion for the signal err looks like this:

assert err='0' report "err/='0' in myUnit" severity error;

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Notes:

  1. Assertions in Verilog can be achieved through SystemVerilog/OVL.

Operations on vectors with aggregate expressions

Say you have eight counters, each giving a status bit telling if it is actively counting or not, and that these status bits are brought together into a bit_vector called isCounting:

signal isCounting: bit_vector(7 downto 0);

Typically, you might want to perform bit operations on such a vector, like OR-ing or AND-ing all the bits, to see if any counter or all counters, respectively, are counting. Assume we want to OR the bits of isCounting into signal atLeastOneIsCounting:

OR into isCounting

This can of course be achieved through a process, e.g.:

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VHDL entity instantiation: why and how

In the days of the ancient Greeks there was component instantiation. Since then (the other parts of) the world has developed and VHDL'93 gave us entity instantiation. Most of you might already be using it, but for those who don't, I'd advise you to keep on reading.

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RLOC attributes on inferred logic

The Xilinx constraint RLOC - relative placement - can be very helpful to improve the timing of timing-critical logic.

There is some struggle involved with getting the RLOC's recognized by the Xilinx tools if we wish to enter them through the HDL and on inferred logic rather than on instantiated primitives.

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