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Operations on vectors with aggregate expressions

Say you have eight counters, each giving a status bit telling if it is actively counting or not, and that these status bits are brought together into a bit_vector called isCounting:

signal isCounting: bit_vector(7 downto 0);

Typically, you might want to perform bit operations on such a vector, like OR-ing or AND-ing all the bits, to see if any counter or all counters, respectively, are counting. Assume we want to OR the bits of isCounting into signal atLeastOneIsCounting:

OR into isCounting

This can of course be achieved through a process, e.g.:

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Hitler uses git

It takes good reasons if I am to link to any of the all-too-many subtitled versions of Hitlers anger outburst.

In this case, good reasons are prevailing. This is the best video I've seen in the genre. However, you'll probably be able to appreciate it only if you're a user of the git Source Code Management System.

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VHDL entity instantiation: why and how

In the days of the ancient Greeks there was component instantiation. Since then (the other parts of) the world has developed and VHDL'93 gave us entity instantiation. Most of you might already be using it, but for those who don't, I'd advise you to keep on reading.

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RLOC attributes on inferred logic

The Xilinx constraint RLOC - relative placement - can be very helpful to improve the timing of timing-critical logic.

There is some struggle involved with getting the RLOC's recognized by the Xilinx tools if we wish to enter them through the HDL and on inferred logic rather than on instantiated primitives.

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Xilinx ISE silent/unattended install

System administrators might find it useful to be able to install Xilinx ISE software silently, without GUI and without having to interact with the install process. This post describes how to use the batch mode installer that Xilinx provides, and how to apply a certain trick needed to make the install truly silent.

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