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Infering dual-port BlockRam with XST

Getting XST (Xilinx' synthesis tool) to infer RAM or ROM that is dual-port requires some tricks.

For some reason, the two ports must be described by separate processes. Furthermore, an unusual VHDL construct, a shared variable, is needed 1.

Below is a listing of my parameterized module for dual-port RAM. It will successfully infer dual-port RAM, as desired, with XST. Remove the write enable-signals and write logic to get ROM instead of RAM. Specify width and depth with width and highAddr (highAddr is one less than desired depth) generics.

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  1. The variable must be accessible through two different processes, and hence must be shared. A signal wouldn't have worked; to implement write-first behaviour in a convenient way, a variable must be used, since the data written must be accessible on the next line of code.

Altera USB-Blaster with Ubuntu 14.04

With some work, I got Alteras on-board USB-Blaster working on my Ubuntu 14.04-64 installation with Quartus II 13.1.0 64-bit. I was connecting to a Terasic SocKit board. In this article, I'll describe how I got it working.

To facilitate working with the Altera software, I suggest adding the bin/ folder of the Quartus installation (/opt/altera/13.1/quartus/bin on my system) to $PATH. This gives command-line access to the commands jtagd and jtagconfig which I use in this post.

Verify USB connection and check Product ID

At first, connect the cable and make sure the USB device is recognized. These are the commands I used and the output I got:

$ dmesg|tail
[16059.962298] usb 2-2: New USB device found, idVendor=09fb, idProduct=6010
[16059.962301] usb 2-2: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[16059.962303] usb 2-2: Product: CV SoCKit
[16059.962305] usb 2-2: Manufacturer: Altera
[16059.962307] usb 2-2: SerialNumber: ARCVSC-123-457
$ lsusb|grep Altera
Bus 002 Device 007: ID 09fb:6010 Altera

Take note of the Product ID listed - 6010 in the above example.

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Getting source highlighting in the Linux terminal

When displaying and grep-ing text in the Linux terminal, syntax highlighting is very nice to have. In this post I'll give my preferred method, with output like:

$ less util.c    # yielding...:

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C: combining assertions with Unit Testing

This is a post that relates to C programming rather than hardware development, for a change.

Two things I'm a big fan of when developing software is designing with assertions (e.g. assert(index >= 0); in C) and Unit Testing (Unit Testing Wikipedia article).

Assertions is available in VHDL as well. I motivate their use in the post Assertions - extending their use and much of that will be valid also in a software context.

This post will describe the way I use to integrate the C assert(...) statements into the test routines utilizing a Unit Testing Framework. I use the CUnit framework but the method will work with any framework.

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Resets - make them synchronous and local

A common approach to resets in a design is to have one single global asynchronous reset network. In this post, I will argue why this is a bad idea, and why you should in fact do the exact opposite, by implementing a reset strategy that is:

  • synchronous - not asynchronous
  • local - not global

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Assertions - extending their use

When designing complex designs, I have come to use assertions more and more often. I've seen their benefits, and in my own design I have tried to get the most out of them by extending their traditional use. I thought I'd share my experiences and thoughts on these matters.

At first some short general notes on assertions. Assertions in VHDL is a means of producing an error at run-time if some condition is not met 1. An assertion for the signal err looks like this:

assert err='0' report "err/='0' in myUnit" severity error;

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  1. Assertions in Verilog can be achieved through SystemVerilog/OVL.

Properly time-distributed stimuli - Part III

A use case example

I was working on a project in which not only the input data was time-stamped, but moreover, the density of the timestamps greatly affected the computation delay in terms of clock cycles. The project was performance critical and careful models of performance were needed. A very careful generation of the time stamps according to an appropriate model was necessary for the simulations to give us the results we needed, and to finally verify our performance models.

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Properly time-distributed stimuli - Part II

Basics about statistical distributions for events random in time

Poisson Process

We will study the case of the input events being described by a Poisson Process, the most common case for events random in time.

Without going into mathematical formalism, roughly described, events adhering to the following conditions can be labeled to be generated by a Poission Process:

  • The time of an event is independent of the time of the previous event
  • The events have a fixed average rate

Some examples of phenomena well-modeled by a Poisson Process are:

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Properly time-distributed stimuli - Part I

Introduction and summary

Finding any bugs or problems in simulations rather than in hardware tests is generally a big time-saver. Some designs will depend on how external input are distributed in time (control signals, input data write/fetches or time-stamped data) and in those cases a good model for those events is sometimes desired.

For events "random in time", we will see that the so-called Poisson Process-related distributions such as the Exponential or the Poisson Distribution can be used. We will also see that time deltas or absolute times of such distributions can be generated rather easily and computing-efficient.

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Xilinx implementation properties for timing performance

Below I have listed the Xilinx implementation properties I use when giving priority to timing rather than area. Settings not mentioned are not as important, or are recommended to be given the default value.

"Exp." means experiment, that is, for that property it might be worth to try with different settings.

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